Previous reports indicated that TSMC is expected to have a producti respsibility for Apple's upcoming A12 chip and its variants. The 7nm node (referred to as CLN7FF, 7FF, or simply N7) is expected to have an approximate 40 percent power and area benefit over TSMC's 10nm FinFET process, used in Apple's A11 processors.
additial, as reported by EETimes TSMC has offered insight into its technology roadmap, both for its silic processes and for its device packaging technologies. TSMC is csidered to be the sole owner of producti for Apple's processors away from the dual-sourcing arrangement with Samsung due to its advancements in wafer-level packaging. (What has been largely unnoticed the TSMC's introducti of land-side capacitors attached directly to the substrate.)
Building the packaging with packaging InFO packaging offerings, TSMC has now announced six new packaging types at a variety of devices and applicatis.
The Technical InFO is getting four cousins. Info-MS, for memory substrate, SoC and HBM packs, a 1x reticle substrate with a 2 x 2-micr redistributi layer and will be qualified in September.
InFO-oS has a backside RDL is better matched to DRAM and is ready now. A multi-stacking opti called MUST e or two chips top of another larger e linked to an interposer at the bottom of the stack.
Finally, InFO-AIP stands for an antenna-in-package, sporting a 10% smaller form factor and 40% higher gain. It targets such designs as frt-end modules for 5G basebands.
But that's not all. TSMC introduced two wholly new packaging optis. A wafer-wafer pack (WoW) directly bds up to three dice. It was released last week, but users need to ensure that their EDA flows support the technical bding. It will get EMI support in June.
Finally, the foundry roughly described something that it called system-integrated-chips (SoICs) using less than 10-micr intercnects to link two dice, but details are still sketchy for the technique to be released sometime next year. It is possible to provide a platform for high-performance computing and can cnect to a number of different devices.
different package and intercnect structures for Apple's SoCs. While InFO offers height, performance and thermal advantages for Apple, they still need to be cnected to the RAM through a package-package cfigurati.
This interface presents thermal challenges and limits the width and speed of the bus interface due to the type of intercnects. The IC industry has made quite a lot of effort in the field of high-bandwidth memory (HBM), but this technology has been relegated to graphics processors at scientific, research, and high performance levels. yield associated with the silic interposers that enable the chip-to-memory cnectis. The fact that TSMC has unveiled a variant of InFO directly in the marketplace.
The InFO-oS process, where the memory bus widths would be much lower, but the per-pin bandwidth is much higher, as seen in LPDDR4. According to a TSMC report, the "oS" porti of this technology refers to -substrate, where die-partitiing would take place.
This would seem to allow for a 2.5D soluti where the memory is in the original. However, the retenti of a redistributi layer is still necessary, but it is still more important than this. While this would eliminate die-stacking, it would increase the total footprint of the packaged soluti, which would still be a ccern in a size-cstrained mobile package.
While Apple could eventually move to an HBM soluti, which affords much greater memory bandwidth to lower power levels, the wafer-wafer (WoW This is a step closer to true 3D integrated circuits, where eventually it would be stacked directly and intercnected through the IC die.
The innovati for TSMC here, and what the interfaces look like, but what type of redistributi layers (RDLs) they offer. While not directly applicable to Apple's line of processors, the InFO-AIP is also an important development, a frt-ends radio frequency (RF) stand-to-stand for amplificati of their standard 5G standards.
Beyd the 7nm node, TSMC also shared its outlook for the foundry's successive nodes, 7nm + and 5nm. 7nm + will be TSMC's first node to feature extreme ultraviolet (EUV) lithography, which stands to simplify the mask process by eliminating the need for multiple patterning in many areas to define smaller features.
Following 7nm + will be 5nm, which would enter risk producti late next year if current timelines hold, meaning volume producti would occur sometime in 2020, but would be too late for a fall in product launch, even with the most optimistic timelines. Though EUV has been lg-awaited and will solve many problems in the industry, it will not be able to do so, nor will it grant as many transitis as 5nm already has its own EUV challenges
The node delivers 35% more speed or uses 65% less power and sports has 3x gain in routed gate density. By ctrast, the N7 + node with EUV will ly deliver 20% more density, 10% less power, and apparently no speed gains – and those progresses
Still, the above news is encouraging, as Apple should be able to enjoy the benefits of a new technology for the next few years. This will offer a boost as its processor architecture gains slow down, and the advent of new packaging techniques will allow.
TSMC has also offered hope for the future, painting the picture beyd 5nm in broad strokes with plans for newer transistor topologies such as silic nanowires, and holes) mobility.
TSMC also describes ways to improve the cductivity and reduce the parasitics associated with the intercnects present in the silic die. Ultimately, these intercnects often dictate how fast transistors can switch over to the effective line load them, and that is all about the way to the package and the PCB. TSMC seems to be diligently pursuing a variety of solutis for its customers, and its packaging solutis are bringing more and more of those compents to the third element.